Fully Asynchronous Reset Recovery Violation
A reset synchronizer safely brings an external asynchronous reset into a local clock domain to prevent recovery time violations.
Expected behavior:
When rst_n is asserted low, the synchronized output rst_sync_n must assert low immediately. When rst_n is de-asserted high, rst_sync_n must remain low until two consecutive rising edges of clk have occurred.
Simulation shows rst_sync_n = 1 immediately when rst_n transitions from 0 to 1 while clk = 0. The reset de-assertion is not synchronized to the clock. Inspect the circuit and correct the fault.
Constraints
- Do not modify the clock source or introduce new clock signals.
- Only use standard D flip-flops with asynchronous clear pins.
- The first flip-flop in the synchronizer chain must have its data input tied high.
Topics
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