Glitchy Reset Source
A reset debouncer ensures that an external noisy reset signal is stable before feeding it to the system reset synchronizer.
Expected behavior:
| Cycle | RST_EXT | RST_DEB | |-------|-----------|-----------| | 1 | 0 | 0 | | 2 | 1 | 0 | | 3 | 0 | 0 | | 4 | 1 | 0 | | 5 | 1 | 0 | | 6 | 1 | 1 | | 7 | 0 | 0 |
Simulation shows RST_DEB = 1 at cycle 2 when RST_EXT asserts for a single clock cycle. The logic is passing transient glitches instead of filtering them. Inspect the circuit and correct the fault.
Constraints
- Do not alter the number of flip-flops in the shift register.
- Maintain synchronous design principles.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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