Gray Code Counter with Non Power of Two Modulus
A modulo-6 Gray code counter generates a sequence of 6 states for clock domain crossing pointers. The counter must preserve the strict Gray code property across all state transitions.
Expected behavior:
| Cycle | rst | gray_out (Binary) | gray_out (Decimal) | |-------|-------|---------------------|----------------------| | 0 | 1 | 001 | 1 | | 1 | 0 | 011 | 3 | | 2 | 0 | 010 | 2 | | 3 | 0 | 110 | 6 | | 4 | 0 | 111 | 7 | | 5 | 0 | 101 | 5 | | 6 | 0 | 001 | 1 |
The testbench reports a CDC violation during the counter wrap-around. After reaching gray_out = 7 (binary 111), the next clock cycle outputs gray_out = 0 (binary 000). This causes three bits to transition simultaneously. Inspect the circuit and correct the fault.
Constraints
- The sequence must contain exactly 6 unique states.
- Exactly one bit must change between any two consecutive states, including the wrap-around.
- The counter must initialize to the first state of the valid sequence when
rst = 1.
Topics
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