Gray Code Counter for Safe Data Transfer
Passing multi-bit counters across clock domains risks sampling intermediate, invalid states. A Gray code sequence ensures only one bit transitions per clock cycle, guaranteeing the receiving domain samples either the old or new valid state safely.
Construct a 3-bit synchronous counter that outputs a standard Gray code sequence. On every rising clock edge, the outputs Q2, Q1, and Q0 must advance to the next state in the sequence. When the synchronous rst signal is 1, the counter must reset to 000.
| Step | Q2 | Q1 | Q0 | |------|------|------|------| | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | | 2 | 0 | 1 | 1 | | 3 | 0 | 1 | 0 | | 4 | 1 | 1 | 0 | | 5 | 1 | 1 | 1 | | 6 | 1 | 0 | 1 | | 7 | 1 | 0 | 0 |
Constraints
- Drive the output signals
Q2,Q1, andQ0directly from the outputs of D flip-flops. - Do not use combinational logic after the flip-flops to decode a standard binary counter.
- Implement a synchronous, active-high reset.
Topics
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