Multi Bit Synchronization Failure
Synchronizing a multi-bit bus with individual 2-flop synchronizers per bit causes fatal synchronization failures when bits resolve on different clock cycles.
Nine signals are shown: CLK (clock, period 2), four asynchronous inputs IN_3, IN_2, IN_1, IN_0, and four synchronized outputs OUT_3, OUT_2, OUT_1, OUT_0. The initial output state is 0011.
Trace all four output signals across the 12 time steps to reveal the intermediate garbage state.
Constraints
- Each output is driven by a standard 2-flop synchronizer triggered on the LOW-to-HIGH transition of
CLK. - The input bus transitions from
0011to1100exactly at the rising edge at time step 3. - Due to routing skew and differing metastability resolution, bits 3 and 1 capture their new values on the rising edge at time step 3.
- Bits 2 and 0 capture their old values at time step 3 and do not capture their new values until the rising edge at time step 5.
Topics
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