Handshake Protocol Timing Analysis
A four-phase handshake coordinates data transfer between two asynchronous clock domains.
Five signals are shown: CLK_A (source clock), CLK_B (destination clock), START (input pulse), REQ (source output, initially 0), and ACK (destination output, initially 0).
REQ updates on every LOW-to-HIGH transition of CLK_A: it is set to 1 if START is 1 and ACK is 0, it is set to 0 if ACK is 1, and otherwise holds its current value. ACK updates on every LOW-to-HIGH transition of CLK_B to match the current value of REQ.
Trace REQ and ACK across all 16 time steps.
Constraints
REQonly changes state exactly on the rising edges ofCLK_A.ACKonly changes state exactly on the rising edges ofCLK_B.- A signal asserted in one domain is not recognized by the other domain until its next rising clock edge.
Topics
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