Acknowledge Signal Generation
Cross-domain data transfers require strict handshake protocols to ensure data integrity. The destination domain must explicitly signal when it has safely captured the payload.
Generate an acknowledge output (ack) based on a synchronized request (req_sync) and a local readiness flag (ready). The circuit must register the ack signal using a synchronous active-high reset (rst). The behavior of the next state for the ack register is defined below:
| rst | req_sync | ready | Current ack | Next ack | |-------|------------|---------|---------------|------------| | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | | 0 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 1 |
Constraints
- Use only basic combinational logic gates and D flip-flops.
- Implement a synchronous active-high reset.
- Do not use latches or asynchronous resets.
Topics
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