Two Phase Handshake Synchronizer
High-throughput clock domain crossing (CDC) interfaces rely on two-phase handshakes to maximize bandwidth. Unlike four-phase protocols that waste clock cycles returning to zero, two-phase protocols signal new events on every signal transition to double the throughput.
The circuit must synchronize incoming asynchronous toggle signals req_in and ack_in into the local clock domain. Route each input through a standard 2-flip-flop synchronizer to mitigate metastability. Detect both rising and falling edges on the synchronized signals. Assert req_valid for exactly one clock cycle when a transition is detected on the synchronized request line, and assert ack_valid for exactly one clock cycle when a transition is detected on the synchronized acknowledge line.
Constraints
- Use only D flip-flops and basic combinational logic gates.
- Implement a standard 2-flip-flop synchronizer for both input lines before edge detection.
- All flip-flops must be clocked by the implicit system clock and cleared by the active-high
rstsignal.
Topics
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