Four Phase Handshake Synchronizer
Reliable data transfer across asynchronous clock boundaries requires strict flow control. A four-phase handshake guarantees data delivery regardless of the frequency ratio between the transmitting and receiving domains.
The circuit consists of a transmitter operating in the clk_a domain and a receiver operating in the clk_b domain. Both domains share an active-high synchronous rst signal.
When the start input is asserted high for one clk_a cycle, the transmitter must assert req high and busy high. The receiver synchronizes req into the clk_b domain using a two-stage flip-flop synchronizer. Upon detecting the synchronized request transitioning high, the receiver asserts ack high and pulses valid high for exactly one clk_b cycle.
The transmitter synchronizes ack back into the clk_a domain. Upon detecting the synchronized acknowledge transitioning high, the transmitter deasserts req low. The receiver synchronizes this low request and subsequently deasserts ack low. Finally, the transmitter synchronizes the low acknowledge and deasserts busy low, completely returning the system to the idle state.
Constraints
- Use two separate state machines: one clocked by
clk_aand one byclk_b. - Use exactly two D-flip-flops for all cross-domain synchronizer chains.
- Drive
reqandackdirectly from flip-flops to prevent glitches during clock domain crossing. - Hold
busyhigh continuously until the entire four-phase sequence completes.
Topics
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