Toggle Pulse Synchronizer

Passing a single-cycle control pulse from a high-speed interface to a slower core domain risks data loss if the pulse falls between slow clock edges. The toggle pulse synchronizer guarantees pulse capture across disparate clock boundaries without the latency penalty of a full request-acknowledge handshake.

Construct a circuit that captures a single-cycle pulse_in synchronized to clk_fast and reproduces it as a single-cycle pulse_out synchronized to clk_slow. The system must operate in three distinct stages:

1. A toggle stage in the fast domain that flips its logical state every time pulse_in is high during a clk_fast rising edge.
2. A dual flip-flop synchronizer that safely passes this toggled level into the slow domain on clk_slow rising edges.
3. An edge detector in the slow domain that asserts pulse_out for exactly one clk_slow cycle whenever the synchronized level changes state.

Constraints

• Use exactly two clock domains: clk_fast for the source stage and clk_slow for the destination stages.
• Implement a standard 2-stage flip-flop synchronizer in the destination domain.
• Use an XOR gate and a delay flip-flop for edge detection in the destination domain.
• Apply the asynchronous active-low reset rst_n to all sequential elements.

Topics

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