Fast to Slow Domain Missed Pulse Analysis
A positive-edge-triggered flip-flop in a slow clock domain captures an unsynchronized pulse from a faster clock domain on every LOW-to-HIGH transition of CLK_SLOW.
Three signals are shown: CLK_SLOW (clock, period 2), PULSE_FAST (input), and Q_SLOW (output, initially 0).
Trace Q_SLOW across all 12 time steps.
Constraints
- The flip-flop evaluates
PULSE_FASTonly whenCLK_SLOWtransitions from 0 to 1. - Any
PULSE_FASTtransition occurring entirely between rising edges ofCLK_SLOWis completely ignored by the output.
Topics
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