Slow to Fast Domain Pulse Synchronization
When passing control signals from a slow peripheral bus to a high-speed processor core, a single-cycle pulse in the slow domain appears as a multi-cycle level in the fast domain. This causes multiple false triggers if not properly converted back to a single pulse.
The circuit receives an asynchronous signal pulse_slow generated in a slower clock domain. It must synchronize this signal into the fast clock domain and output a single-cycle pulse pulse_fast for every rising edge of the synchronized signal. The system uses an active-high asynchronous reset rst.
| Cycle | rst | pulse_slow | pulse_fast | |-------|-------|--------------|--------------| | 1 | 1 | 0 | 0 | | 2 | 0 | 1 | 0 | | 3 | 0 | 1 | 1 | | 4 | 0 | 1 | 0 | | 5 | 0 | 0 | 0 |
Constraints
- Use a two-stage flip-flop synchronizer to cross the clock domain.
- Implement a rising-edge detector immediately following the synchronizer.
- Assert the output
pulse_fastfor exactly one clock cycle per slow domain pulse. - Clock all flip-flops using the implicit fast domain clock.
- Connect all flip-flops to the asynchronous active-high reset
rst.
Topics
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