Fast to Slow Domain Level Synchronization
Configuration signals often originate in a high-speed processor domain and travel to slower peripheral blocks. Because these control levels are held indefinitely, complex handshaking is unnecessary to safely cross the clock boundary.
Route the incoming asynchronous signal sig_fast into the clk_slow domain. The output sig_slow must output the stable level of sig_fast after resolving potential metastability. Assuming all flip-flops initialize to 0, the propagation sequence must match the following behavior:
| clk_slow | sig_fast | sig_slow | |------------|------------|------------| | 0 | 1 | 0 | | 1 | 1 | 0 | | 0 | 1 | 0 | | 1 | 1 | 1 | | 0 | 0 | 1 | | 1 | 0 | 1 | | 0 | 0 | 1 | | 1 | 0 | 0 |
Constraints
- Use exactly two D flip-flops.
- Connect both flip-flop clock pins directly to
clk_slow. - Do not use any combinational logic gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.