Slow to Fast Domain Level Synchronization
Configuration registers and static control signals often originate in a slow management domain and must be read by a high-speed processing core. Moving a static or slow-changing level into a faster clock domain requires mitigating metastability without risking data loss.
Route the asynchronous input async_in through two cascaded D flip-flops to produce the synchronized output sync_out. Both flip-flops must be clocked by the destination domain clock and reset to 0 by the synchronous rst signal. Because the source domain is slower than the destination domain, the fast clock guarantees multiple sampling edges per data phase. This ensures the static signal is captured safely without requiring a complex handshake protocol.
Constraints
- Use exactly two D flip-flops.
- Clock both flip-flops with the destination domain clock.
- Connect the synchronous
rstsignal to the reset port of both flip-flops. - Do not use any combinational logic gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.