Handshake with Mismatched State Machines
A fully interlocked handshake protocol ensures safe data transfer across clock domains. The source state machine asserts REQ to initiate a transfer and waits for the destination to assert ACK. Once ACK is received, the source deasserts REQ and must wait for ACK to return to zero before initiating the next transfer.
Expected behavior:
| Current State | Start | ACK | REQ | Done | Next State | |---------------|---------|-------|-------|--------|------------| | IDLE | 0 | X | 0 | 0 | IDLE | | IDLE | 1 | X | 0 | 0 | REQUEST | | REQUEST | X | 0 | 1 | 0 | REQUEST | | REQUEST | X | 1 | 1 | 1 | WAIT_LOW | | WAIT_LOW | X | 1 | 0 | 0 | WAIT_LOW | | WAIT_LOW | X | 0 | 0 | 0 | IDLE |
Simulation of back-to-back transfers shows the source domain registering a second completed transfer prematurely. When a new transfer is initiated while ACK is still high from the previous cycle, the source domain outputs Done = 1 again instead of waiting for ACK to drop. Inspect the circuit and correct the fault.
Constraints
- You must only modify the state transition logic of the source domain.
- Do not add new input or output ports.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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