Implicit Wire Creation from Typo
A 32-bit address pipeline stage buffers the memory address between the fetch and decode phases.
Expected behavior: The 32-bit output addr_out must exactly match the 32-bit input addr_in after the pipeline register updates.
Simulation shows addr_out = 1 for input addr_in = 4294967295. For input addr_in = 4096, the output evaluates to addr_out = 0. The upper 31 bits are lost during the transfer. Inspect the circuit and correct the fault.
Constraints
- Do not change the module interface or port widths.
- Do not add new modules or primitives.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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