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Codiode/Problems/Sequential Logic

Incomplete Case Statement

EasyLogic CircuitDebug

A seven segment display decoder converts a 4-bit binary input into signals that drive a 7-segment LED display.

Expected behavior:

The circuit must output the standard segment patterns for inputs 0 through 9. For inputs 10 through 15, all segment outputs must be 0.

| D3 | D2 | D1 | D0 | a | b | c | d | e | f | g | |------|------|------|------|-----|-----|-----|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

Simulation shows that when the input transitions from 9 (D3=1, D0=1) to 10 (D3=1, D1=1), the outputs remain at a=1, b=1, c=1, d=1, e=0, f=1, g=1. The circuit is retaining its previous state for undefined inputs. Inspect the circuit and correct the fault.

Constraints

  • Do not add new input or output pins.
  • The circuit must be entirely combinational with no inferred memory.

Topics

debuglatchessequential-logic

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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