JK Master-Slave: 1s-Catching Problem
A pulse-triggered master-slave JK flip-flop suffers from a historical silicon bug known as ones-catching: any brief assertion of an input during the clock's HIGH phase is captured by the master latch and transferred to the output on the falling edge.
Four signals are shown: CLK (clock, HIGH for 4 time units, LOW for 4 time units), J (set input), K (reset input), and Q (output, initially 0). The J input pulses HIGH briefly while CLK is HIGH and returns to LOW before the clock's falling edge. The K input similarly pulses HIGH during the second clock cycle. Unlike a modern edge-triggered flip-flop which ignores mid-cycle glitches, this circuit captures the transient state.
Trace Q across all 16 time steps to demonstrate the ones-catching behavior.
Constraints
Qonly updates its state on the HIGH-to-LOW transition ofCLK.- The master latch evaluates
JandKcontinuously whileCLKis HIGH. - Once the master latch sets or resets during a HIGH clock phase, it cannot be reverted until the next clock cycle.
Topics
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