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Codiode/Problems/Sequential Logic

Johnson Counter: Glitch-Free 8-Phase Decode

MediumLogic CircuitBuild

High-speed state machines and multiphase clock generators require control signals that transition without intermediate transient spikes. A 4-bit Johnson counter provides this property by changing only one bit per state transition, allowing glitch-free decoding of all 8 phases using simple two-input logic gates.

Construct the combinational decode logic that takes the 4-bit Johnson counter state (Q3, Q2, Q1, Q0) and asserts exactly one of the eight phase outputs (P0 through P7) HIGH.

| Q3 | Q2 | Q1 | Q0 | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |------|------|------|------|------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |

Constraints

  • Use exactly two inputs per phase decode logic gate.
  • Derive the logic using only 2-input AND or AND-NOT configurations.
  • Implement combinational logic only.

Topics

Shift RegistersDecodeGlitch-Free

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