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Codiode/Problems/Sequential Logic

Johnson Counter: Glitch-Free Decode

MediumLogic CircuitTiming Diagram

A 4-bit Johnson counter cycles through states where only one bit changes per clock cycle, allowing each state to be decoded without glitches using simple 2-input logic gates.

Seven signals are shown: CLK (clock, period 2), Q3, Q2, Q1, and Q0 (inputs representing the counter state), and DEC1 and DEC2 (outputs, initially 0).

Trace the combinational outputs DEC1 (defined as Q0 AND NOT Q1) and DEC2 (defined as Q1 AND NOT Q2) across all 12 time steps.

Constraints

  • DEC1 must be evaluated strictly as the boolean expression Q0 & ~Q1.
  • DEC2 must be evaluated strictly as the boolean expression Q1 & ~Q2.

Topics

combinational-logiccountersdecoding

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