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Codiode/Problems/Sequential Logic

4-Bit Johnson Counter: Full Sequence Trace

EasyLogic CircuitTiming Diagram

A 4-bit positive-edge-triggered Johnson counter shifts its state rightward while feeding the inverted output of its final stage back to the input of its first stage.

Five signals are shown: CLK (clock, period 2), and the sequential stage outputs Q0, Q1, Q2, and Q3 (all initially 0).

Trace Q0, Q1, Q2, and Q3 across all 16 time steps to reveal the complete 8-state sequence.

Constraints

  • Output changes only occur on the LOW-to-HIGH transition of CLK.
  • The next state of Q0 is the inverse of the current state of Q3.
  • The next state of Q[N] is the current state of Q[N-1].

Topics

Timing DiagramCountersJohnson Counter

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