4-Bit Johnson Counter: Basic Construction
Multiphase clock generators and glitch-free decoders rely on counters that change only one bit at a time. The 4-bit Johnson counter uses inverted feedback to double the state count of a standard ring counter, producing an 8-state sequence.
On each rising edge of clk, the counter shifts its state to the right. The inverted output of the final stage must feed back into the input of the first stage. An asynchronous active-high rst signal clears all outputs to 0.
| clk edge | Q3 | Q2 | Q1 | Q0 | |------------|------|------|------|------| | Initial | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | | 2 | 0 | 0 | 1 | 1 | | 3 | 0 | 1 | 1 | 1 | | 4 | 1 | 1 | 1 | 1 | | 5 | 1 | 1 | 1 | 0 | | 6 | 1 | 1 | 0 | 0 | | 7 | 1 | 0 | 0 | 0 | | 8 | 0 | 0 | 0 | 0 |
Constraints
- Use exactly four D flip-flops.
- Drive all flip-flops with the same
clkandrstsignals. - Connect the inverted output of the final stage to the input of the first stage.
Topics
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