BCD Counter: 3-Stage Cascade
Digital clocks, instrumentation panels, and frequency meters rely on decimal counting stages to drive multi-digit displays. A cascaded Binary-Coded Decimal (BCD) counter tracks values from 000 to 999 and signals a rollover to subsequent higher-order modules.
Implement a 3-stage BCD counter using a single global clock. The counter must support a synchronous active-high reset rst and an enable signal en. The output consists of three 4-bit buses: Q_ones, Q_tens, and Q_hundreds. Each stage counts from 0 to 9.
The Q_tens stage must only increment when Q_ones is at 9 and en is high. The Q_hundreds stage must only increment when both Q_tens and Q_ones are at 9 and en is high. The global carry-out CO must assert high only when the entire counter is at 999 and en is active.
Constraints
- Use a single global clock for all sequential elements.
- Implement synchronous active-high reset logic for all stages.
- Gate the carry-out of each stage with the enable condition of the previous stages.
- Do not chain carry-outs directly to the clock pins of subsequent stages.
- Output values for
Q_ones,Q_tens, andQ_hundredsmust never exceed 9.
Topics
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