BCD Counter: Synchronous vs. Asynchronous Reset
A digital display uses a BCD counter that detects the invalid state 10: a synchronous reset holds the '10' state until the next clock cycle, while an asynchronous reset clears it immediately.
Five signals are shown: CLK (clock, period 2), EN (count enable), LOAD9 (synchronous load), DISP_SYNC (output, initially 0), and DISP_ASYNC (output, initially 0).
Both counters begin at state 8. On the LOW-to-HIGH transition of CLK, if LOAD9 is 1 the state becomes 9, otherwise if EN is 1 the state increments by 1.
When a counter reaches state 10, its display output (DISP_SYNC or DISP_ASYNC) becomes 1. The synchronous counter resets to 0 on the next rising edge of CLK, overriding LOAD9 and EN. The asynchronous counter resets to 0 on the very next time step, independent of CLK.
Trace DISP_SYNC and DISP_ASYNC across all 16 time steps.
Constraints
DISP_SYNCandDISP_ASYNCare binary signals (0 or 1).- The asynchronous reset takes effect exactly one time step after the state becomes 10.
- The synchronous reset takes effect exactly on the next rising edge of
CLK.
Topics
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