BCD Counter: 7-Segment Decoder Integration
Digital clocks, multimeters, and industrial control panels rely on direct numeric readouts for human-machine interfaces. The BCD-to-7-segment subsystem translates a continuous clock pulse into a stable, base-10 visual output.
The circuit must increment its internal binary-coded decimal state from 0 to 9 on each rising edge of clk. Upon reaching 9, the next rising edge of clk must wrap the state back to 0. When the synchronous rst signal is high, the internal state must clear to 0 on the next rising clock edge.
The 7-bit output seg must continuously drive an active-high 7-segment display corresponding to the current state. The bit mapping for seg[6:0] is: bit 6 is g, bit 5 is f, bit 4 is e, bit 3 is d, bit 2 is c, bit 1 is b, and bit 0 is a.
The table below shows the required active-high segment encoding for the critical boundary values:
| Internal State | Active Segments | seg[6:0] (Binary) | seg (Decimal) | |----------------|-----------------|---------------------|-----------------| | 0 | a,b,c,d,e,f | 0111111 | 63 | | 1 | b,c | 0000110 | 6 | | 8 | a,b,c,d,e,f,g | 1111111 | 127 | | 9 | a,b,c,d,f,g | 1101111 | 111 |
Constraints
- Implement a synchronous reset that clears the internal counter to 0.
- The output must not glitch into hexadecimal values during the transition from 9 to 0.
- Use active-high logic for the
segoutput.
Topics
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