Johnson Counter: One Flip-Flop Stuck at 0
A 4-bit Johnson counter generates an 8-state sequence by shifting bits and feeding the inverted output of the last stage back to the first.
Expected behavior:
| Clock Cycle | Q0 | Q1 | Q2 | Q3 | |-------------|------|------|------|------| | 0 (Reset) | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 0 | | 3 | 1 | 1 | 1 | 0 | | 4 | 1 | 1 | 1 | 1 | | 5 | 0 | 1 | 1 | 1 | | 6 | 0 | 0 | 1 | 1 | | 7 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 |
Simulation shows that after resetting to 0000, the counter progresses to 1000 and 1100, but then remains locked at 1100 for all subsequent clock cycles. The expected state 1110 at clock cycle 3 is never reached. Inspect the circuit and correct the fault.
Constraints
- Maintain the 4-bit shift register architecture.
- Do not add new flip-flops to the circuit.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.