Latch vs Clock Enable Inference
Hardware synthesis tools infer completely different physical components from identical logical constructs depending on the process sensitivity list.
The snippet provided shows two Verilog blocks side by side. Block A uses an always_comb block with an incomplete if statement assigning a data input to out_a. Block B uses an always_ff @(posedge clk) block with the exact same incomplete if statement assigning a data input to out_b. Both blocks rely on the same condition signal en.
Analyze the synthesis behavior for both blocks. Determine the inferred hardware structures and trace the data paths for out_a and out_b under various en conditions.
Constraints
- Assume standard synthesis tool behavior matching IEEE 1364/1800 specifications.
- All signals are 1-bit wide.
- The data input is assumed to be synchronous to
clkfor Block B.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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