LFSR as a Counter: 4-Bit Maximal-Length Sequence
Pseudo-random bit sequences (PRBS) and cyclic redundancy checks (CRC) rely on linear feedback shift registers to generate maximal-length sequences with minimal hardware. The 4-bit LFSR acts as a pseudo-random address counter that cycles through 15 unique non-zero states.
Implement a 4-bit LFSR using the primitive polynomial x^4 + x + 1. The circuit maintains a 4-bit state represented by outputs Q3 (MSB), Q2, Q1, and Q0 (LSB).
On every rising clock edge, the register shifts right. The feedback is generated by XORing specific taps: * Q2 receives the value of Q3. * Q1 receives the value of Q2. * Q0 receives the value of Q1. * Q3 receives the feedback value: Q3 XOR Q0.
When rst is 1, the state must synchronously reset to 0001 (Q3=0, Q2=0, Q1=0, Q0=1) to prevent initialization into the all-zeros lockup state.
Constraints
- Use exactly four D flip-flops.
- Use only XOR gates for the feedback path.
- The
rstsignal must act synchronously on the clock edge. - Do not implement self-correction logic for the
0000lockup state.
Topics
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