Master-Slave D Flip-Flop from NAND Latches
Every positive-edge-triggered D flip-flop in a chip is physically implemented as a master-slave pair of level-sensitive latches. The master latch captures the D input while the clock is low (transparent when CLK=0). The slave latch captures the master's output while the clock is high (transparent when CLK=1). Because the master closes before the slave opens, data propagates through exactly once per clock edge — this is the mechanism behind edge-triggering. Understanding this structure is mandatory for timing-closure interviews at Intel, Qualcomm, and AMD.
Your task is to build a positive-edge-triggered D flip-flop from scratch using exactly 10 NAND2 gates — no DFF component allowed. The master latch is a clocked NAND SR-latch enabled by NOT(CLK), and the slave latch is a clocked NAND SR-latch enabled by CLK. The output Q of the flip-flop changes only on the rising edge of CLK.
The structural breakdown: a clocked NAND D-latch requires 4 NAND gates (one to invert D, one to AND CLK with D, one to AND CLK with NOT_D, plus two cross-coupled NAND gates for the SR core). Two such latches share one NOT(CLK) gate, giving 4 + 4 + 2 = 10 total NAND gates. The master uses NOT(CLK) as its enable; the slave uses CLK directly.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | D | input | 1 | Data input | | CLK | input | 1 | Clock signal; Q captures D on the rising edge (0 to 1 transition) | | Q | output | 1 | Flip-flop output: updates on positive CLK edge |
Constraints
- Only NAND2 gates are allowed. No DFF, AND, OR, NOT, XOR, or NOR components.
- Exactly 10 NAND2 gates are required for the optimal solution.
- The master latch must be transparent when CLK=0 (tracking D when clock is low).
- The slave latch must be transparent when CLK=1 (tracking master output when clock is high).
- Q must be stable when CLK is high after the rising edge — the slave latch holds the captured value.
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