Master-Slave DFF: Both Enables Same Polarity Debug
A master-slave D flip-flop provides reliable edge-triggered state storage for synchronous digital systems.
Expected behavior:
The output Q should only update to match the input D on the falling edge of the clock signal CLK. At all other times, Q must hold its previous state regardless of changes to D.
Simulation shows timing violations during the high phase of the clock. When CLK is 1, changing D from 0 to 1 causes Q to immediately change to 1. The output fails to hold its state and acts as a transparent latch instead of an edge-triggered device.
Inspect the circuit and correct the fault.
Constraints
- Do not replace the entire circuit with a primitive DFF component.
- Only modify the existing gate-level implementation to fix the fault.
- Do not add external clock edge-detection circuitry.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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