Master-Slave vs. Edge-Triggered DFF: Glitch Rejection Comparison
Legacy master-slave flip-flops suffer from "1s-catching" where glitches during the high clock phase corrupt the captured state, a flaw solved by modern edge-triggered designs. Four signals are shown: CLK (clock, period 2), D (input data), Q_MS (legacy pulse-triggered output, initially 0), and Q_EDGE (modern edge-triggered output, initially 0). Q_MS captures a 1 if D is 1 at any point while CLK is 1, and updates its output on the step CLK transitions LOW. Q_EDGE samples D from the step immediately prior to CLK transitioning HIGH, and updates its output on the step CLK transitions HIGH. Trace both Q_MS and Q_EDGE across all 12 time steps.
Constraints
Q_MSupdates its output only on the stepCLKtransitions from 1 to 0.Q_EDGEupdates its output only on the stepCLKtransitions from 0 to 1.- If
Dis 1 during any step whereCLKis 1, the master stage ofQ_MScatches it and will output 1 on the subsequent falling edge.
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