Edge-Triggered DFF from 3 NAND Latches
Standard cell libraries rarely use master-slave latches for their flip-flops. The industry standard commercial D-flip-flop relies on a three-latch arrangement to eliminate transparency and improve setup and hold times.
Implement a positive edge-triggered D flip-flop using the Sutherland-style 3-latch configuration. The circuit must capture D exactly on the rising edge of CLK and hold the state steady at all other times.
| CLK | D | Q | Qn | |-------|-----|-----|------| | 0 | X | No change | No change | | Rise | 0 | 0 | 1 | | Rise | 1 | 1 | 0 | | 1 | X | No change | No change |
Constraints
- Use exactly six NAND gates.
- Do not use any structural DFF or latch primitives.
- The output must not change when
Dtransitions whileCLKis steady high or steady low.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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