Master-Slave: Internal Node Propagation
A standard master-slave flip-flop consists of two cascaded level-sensitive latches: the master tracks the input when the clock is HIGH, and the slave tracks the master when the clock is LOW. Four signals are shown: CLK (clock, period 4), D (input), Q_master (internal master output, initially 0), and Q_slave (final slave output, initially 0). Trace both Q_master and Q_slave across all 12 time steps.
Constraints
Q_mastertracksDwhileCLKis 1 and holds its previous value whileCLKis 0.Q_slavetracksQ_masterwhileCLKis 0 and holds its previous value whileCLKis 1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.