DFF with Active-Low Asynchronous Reset: Construction
Microcontrollers and system-on-chip designs rely on reliable initialization states to prevent erratic behavior at power-up. An asynchronous reset forces the storage element to a known state immediately upon assertion, completely independent of the clock signal.
The circuit must capture the input D on the rising edge of CLK when RST_bar is 1. When RST_bar is 0, the output Q must become 0 instantly, overriding any clock or data activity.
| RST_bar | CLK | D | Q | |-----------|-------|-----|-----| | 0 | X | X | 0 | | 1 | 0 -> 1| 0 | 0 | | 1 | 0 -> 1| 1 | 1 | | 1 | 0 | X | Hold| | 1 | 1 | X | Hold|
Constraints
- Build the circuit using only basic logic gates.
- Do not use pre-built flip-flop or latch primitives.
- Implement an asynchronous reset path that bypasses the clock dependency.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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