Asynchronous Reset: Immediate Q Clearing Between Clock Edges

EasyLogic CircuitTiming Diagram

A positive-edge-triggered D flip-flop with an active-low asynchronous reset clears its output immediately when the reset signal is asserted, regardless of the clock state.

Three input signals are shown: CLK (clock, period 2), RST_bar (active-low asynchronous reset), and D (data input). Assume zero propagation delay.

Trace the output signal Q across all 10 time steps, starting with an initial value of 0.

Constraints

The output Q must transition to 0 at the exact time step RST_bar becomes 0.
When RST_bar is 1, Q only captures the value of D on the LOW-to-HIGH transition of CLK.
A clock edge occurring while RST_bar is 0 is ignored.

Topics

Latches and Flip-FlopsAsynchronous ResetDFFTiming Analysis

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Asynchronous Reset: Immediate Q Clearing Between Clock Edges

EasyLogic CircuitTiming Diagram

A positive-edge-triggered D flip-flop with an active-low asynchronous reset clears its output immediately when the reset signal is asserted, regardless of the clock state.

Three input signals are shown: CLK (clock, period 2), RST_bar (active-low asynchronous reset), and D (data input). Assume zero propagation delay.

Trace the output signal Q across all 10 time steps, starting with an initial value of 0.

Constraints

The output Q must transition to 0 at the exact time step RST_bar becomes 0.
When RST_bar is 1, Q only captures the value of D on the LOW-to-HIGH transition of CLK.
A clock edge occurring while RST_bar is 0 is ignored.

Topics

Latches and Flip-FlopsAsynchronous ResetDFFTiming Analysis

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Asynchronous Reset: Immediate Q Clearing Between Clock Edges

Constraints

Topics

Solve this problem

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Asynchronous Reset: Immediate Q Clearing Between Clock Edges

Constraints

Topics

Solve this problem

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