DFF with Active-High Asynchronous Reset: Gate-Level Polarity Conversion
Control logic and state machines frequently interface with varying signal polarities across different IP blocks. A standard D flip-flop must be adapted to respond to an active-high reset signal while maintaining its standard edge-triggered data capture.
The circuit must implement a positive edge-triggered D flip-flop with an asynchronous active-high reset. When RST is 1, the output Q must immediately become 0 regardless of the clock CLK. When RST is 0, the flip-flop captures the value of D on the rising edge of CLK.
| RST | CLK | D | Q | |-------|-------|-----|-----| | 1 | X | X | 0 | | 0 | ↑ | 0 | 0 | | 0 | ↑ | 1 | 1 | | 0 | 0/1 | X | hold|
Constraints
- Use only basic logic gates (NAND, NOR, AND, OR, NOT).
- Do not use pre-built sequential elements or flip-flop macros.
- Ensure the reset operation is fully asynchronous and does not wait for a clock edge.
Topics
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