DFF with Both PRE and CLR
Standard discrete logic families like the 74HC74 provide flip-flops with both asynchronous preset and clear inputs. These inputs allow external events to force the state of the flip-flop regardless of the clock signal, serving as critical initialization and reset mechanisms in digital systems.
The circuit must function as a positive-edge triggered D flip-flop when both asynchronous controls are inactive. An active-low PRE_bar immediately forces Q to 1. An active-low CLR_bar immediately forces Q to 0. If both are asserted simultaneously, both Q and Q_bar are driven to 1. This is a forbidden state in normal operation but must be explicitly handled by the internal gate structure to match standard hardware behavior.
| PRE_bar | CLR_bar | CLK | D | Q | Q_bar | |-----------|-----------|-------|-----|-----|---------| | 0 | 0 | X | X | 1 | 1 | | 0 | 1 | X | X | 1 | 0 | | 1 | 0 | X | X | 0 | 1 | | 1 | 1 | ↑ | 0 | 0 | 1 | | 1 | 1 | ↑ | 1 | 1 | 0 |
Constraints
- Construct the flip-flop using only basic logic gates.
- Do not use pre-built flip-flop or latch macros.
- Ensure the simultaneous active state drives both outputs high without oscillation.
Topics
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