Asynchronous Reset: Reset Recovery Time Violation
A positive-edge-triggered D flip-flop with an asynchronous active-low reset requires the reset signal to deassert at least 2 time steps before the clock edge to avoid metastability. Four signals are shown: CLK (clock, period 4), RST_bar (active-low asynchronous reset), D (input), and Q (output, initially 0). Trace Q across all 16 time steps, using X for any cycle where a recovery time violation causes an indeterminate state.
Constraints
RST_barasynchronously forcesQto 0 when LOW, overriding all other inputs.- A recovery time violation occurs if
RST_bartransitions from LOW to HIGH less than 2 time steps before a LOW-to-HIGH transition ofCLK. - If a recovery time violation occurs,
Qbecomes indeterminate (X) at the clock edge and remainsXuntil the next valid clock edge.
Topics
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