DFF with Asynchronous Reset and Clock Enable
Modern digital systems aggressively use clock gating and reset domains to manage power and state. Combining an asynchronous reset with a synchronous clock enable creates a robust storage element that can be initialized instantly while selectively holding data during operation.
The circuit updates the output Q to the value of D on the rising edge of CLK only when CE is 1. If CE is 0, Q retains its current state. The asynchronous, active-low reset RST_bar forces Q to 0 immediately. This reset action overrides all other inputs and clock events.
| RST_bar | CLK | CE | D | Q (next) | |-----------|-------|------|-----|------------| | 0 | X | X | X | 0 | | 1 | ↑ | 1 | 0 | 0 | | 1 | ↑ | 1 | 1 | 1 | | 1 | ↑ | 0 | X | Q (prev) | | 1 | 0/1 | X | X | Q (prev) |
Constraints
- Implement using a standard D flip-flop primitive and basic logic gates or multiplexers.
- The reset path must be strictly asynchronous and act independently of the clock.
- Do not use latches.
- Do not modify the clock signal path.
Topics
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