Asynchronous Reset Release: Which Cycle Does Q Recover?
A positive-edge-triggered D flip-flop with an active-low asynchronous reset forces its output to 0 immediately when reset is asserted, but resumes normal edge-triggered capture only at the next clock edge after reset is released. Three signals are provided: CLK (clock, period 8), RST_bar (active-low asynchronous reset input), and D (data input). Trace the output signal Q across all 16 time steps given an initial state of 1.
Constraints
RST_baris active-low: it forcesQto 0 immediately at the exact time step it transitions to 0, overriding all other inputs.- When
RST_bartransitions to 1 (deasserts),Qdoes not capture the current value ofDimmediately. - The flip-flop only captures
Don a LOW-to-HIGH transition ofCLKwhileRST_baris 1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.