DFF with Synchronous Active-Low Reset
Synchronous reset networks ensure that reset assertions and de-assertions are fully timed, preventing metastability across clock domains. An active-low synchronous reset forces the flip-flop state to zero strictly on the next positive clock edge, ignoring mid-cycle toggles.
| clk | RST_bar | D | Q (next) | |-------|-----------|-----|------------| | ↑ | 0 | X | 0 | | ↑ | 1 | 0 | 0 | | ↑ | 1 | 1 | 1 | | 0/1 | X | X | Q (prev) |
Constraints
- Use a standard D flip-flop and combinational logic gates.
- Do not connect
RST_barto any asynchronous clear or preset ports on the flip-flop. - Reset logic must be implemented exclusively in the data input path.
Topics
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