Mealy Output Combinational Loop
A bus arbiter and requester pair manages shared bus access.
Expected behavior:
| Cycle | Start | Req | Grant | |-------|---------|-------|---------| | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | | 3 | 0 | 0 | 1 | | 4 | 0 | 0 | 0 |
Simulation halts with a combinational loop error during Cycle 2. The synthesis logs report a zero-delay circular dependency between Req and Grant. Inspect the circuit and correct the fault.
Constraints
- Ensure the arbiter output is properly registered.
- Do not alter the requester's combinational logic.
- Maintain the exact cycle timing shown in the expected behavior table.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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