Min Max Finder
Sorting networks, median filters in image processing, and high-speed decision logic often require finding the extreme values among a set of inputs in a single clock cycle. Sequential loops are too slow for these data-streaming applications, necessitating a purely combinational datapath that can evaluate all candidates simultaneously.
This module evaluates four independent 8-bit unsigned integer inputs. It combinationally compares these four values and routes the smallest value to the minimum output port and the largest value to the maximum output port.
Because this is a purely combinational circuit, there are no clock or reset signals. The outputs must update immediately in response to any input change.
Example Trace: • a=10, b=20, c=30, d=40 → min_val=10, max_val=40 • a=200, b=50, c=200, d=10 → min_val=10, max_val=200 • a=255, b=255, c=255, d=255 → min_val=255, max_val=255
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | First unsigned input value | | b | input | 8 | Second unsigned input value | | c | input | 8 | Third unsigned input value | | d | input | 8 | Fourth unsigned input value | | min_val | output | 8 | The smallest value among the four inputs | | max_val | output | 8 | The largest value among the four inputs |
Constraints
- The circuit must be purely combinational. Do not infer any latches or flip-flops.
- All inputs and outputs are treated as 8-bit unsigned integers.
- If multiple inputs share the same minimum or maximum value, the output must simply reflect that value.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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