Moving Average Filter Combinational
Signal processing pipelines frequently rely on moving average filters to smooth out high-frequency noise from sensor data. This module computes the arithmetic mean of four concurrent 8-bit data samples in a single clock cycle equivalent.
Hardware division using a general-purpose divider is highly resource-intensive. However, since the number of samples in this filter is exactly four (a power of two), the division must be implemented efficiently as a right shift. To prevent a systematic downward bias in the filtered output, the design must perform proper rounding rather than simple truncation. This is mathematically achieved by adding half the divisor to the sum before shifting the bits.
This is a purely combinational circuit. Changes on any input must immediately reflect on the output without waiting for a clock edge.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | s0 | input | 8 | Data sample 0 | | s1 | input | 8 | Data sample 1 | | s2 | input | 8 | Data sample 2 | | s3 | input | 8 | Data sample 3 | | avg | output | 8 | Rounded arithmetic mean of the four samples |
Constraints
- Purely combinational logic; no flip-flops, registers, or latches are permitted.
- All inputs and the output are 8-bit unsigned integers.
- Internal arithmetic must use sufficient bit width to prevent overflow before the final division step.
- The division step must be implemented via bit-shifting rather than a division operator.
- The result must be rounded to the nearest integer by adding half the divisor prior to the shift.
Topics
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