Minimum FIFO Depth Calculation
Asynchronous FIFOs buffer data between clock domains with differing frequencies to prevent data loss. An oversized FIFO wastes silicon area, while an undersized FIFO chokes system throughput. An architecture specifies a write clock wr_clk operating at 500 MHz and a read clock rd_clk operating at 200 MHz. The system guarantees a maximum write burst size of 128 words. During a burst, data is written on every cycle of wr_clk. The read side consumes one word on every cycle of rd_clk continuously. Determine the minimum FIFO depth required to prevent a full condition and avoid stalling the transmitter.
Constraints
wr_clkoperates at exactly 500 MHz.rd_clkoperates at exactly 200 MHz.- The maximum continuous write burst is exactly 128 words.
- The read interface consumes data continuously with no idle cycles once data is available.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.