Minimum Pulse Width: Setup Plus Hold Constraint
Synchronizing short asynchronous pulses like interrupts or button presses requires strict timing to ensure the receiving flip-flop can reliably capture the event. A signal must remain stable through a specific window of time around the clock edge to avoid metastability.
A rising-edge triggered D flip-flop receives an asynchronous data pulse on input D and is clocked by signal CLK. The flip-flop has a setup time t_setup of 2 time units and a hold time t_hold of 1 time unit. The clock period is significantly longer than the pulse width.
Evaluate the minimum pulse width required on D to prevent the pulse from being completely swallowed by the timing requirements. Identify the alignment scenarios that cause timing violations.
Constraints
t_setupis exactly 2 time units.t_holdis exactly 1 time unit.- The asynchronous pulse on
Darrives randomly relative to the active edge ofCLK.
Topics
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