Mismatched Routing Delays on Gray Codes
A Gray code pointer safely transfers multi-bit state across clock domains by ensuring only one bit transitions at a time.
Expected behavior:
The 2-bit synchronized pointer ptr_sync must follow the exact Gray code sequence 00, 01, 11, 10 across clock domain boundaries.
Post-layout simulation shows an invalid state transition. When the source domain transitions from 01 to 11, the destination domain samples 00 for one clock cycle before settling on 11. The RTL logic passes functional verification but fails timing-aware simulation.
Inspect the circuit and correct the fault.
Constraints
- Do not modify the underlying RTL logic.
- Apply the fix strictly to the timing constraint file.
- The solution must constrain the routing delay difference across the bus to be less than the destination clock period.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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