Mod-60 Counter: Tens Digit Wrong Modulus Debug
A Mod-60 counter tracks seconds and minutes in digital clocks by cascading a mod-10 ones digit and a mod-6 tens digit.
Expected behavior:
The counter increments on each active clock edge when En is high. When the count reaches 59 (Tens = 5, Ones = 9), the next clock pulse must roll the count over to 00 (Tens = 0, Ones = 0). Asserting Rst asynchronously clears both digits to 0.
Simulation shows the count reaching 75 (Tens = 7, Ones = 5) instead of rolling over after 59. The counter sequence fails to reset at the correct modulus.
Inspect the circuit and correct the fault.
Constraints
- Do not modify the ones digit counter.
- Only replace or rewire the faulty component to restore the correct modulus.
- The
TensandOnesoutputs must remain 4-bit wide.
Topics
Solve this problem
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