Mod-N Counter: Off-by-One in Terminal Count Detection Debug
A Mod-5 counter generates a repeating sequence of five states from 0 to 4. It uses a synchronous reset to return to 0 after reaching the terminal count.
Expected behavior:
| Clock Cycle | rst | Q2 | Q1 | Q0 | State (Decimal) | |-------------|-------|------|------|------|-----------------| | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 1 | | 2 | 0 | 0 | 1 | 0 | 2 | | 3 | 0 | 0 | 1 | 1 | 3 | | 4 | 0 | 1 | 0 | 0 | 4 | | 5 | 0 | 0 | 0 | 0 | 0 |
Simulation shows the counter sequences through 0, 1, 2, 3, 4, and 5. The outputs Q2, Q1, and Q0 reach a value of 5 (101) before resetting to 000 on the subsequent clock cycle. The modulo period is incorrect. Inspect the circuit and correct the fault.
Constraints
- Do not replace the flip-flops.
- Modify only the combinational logic driving the synchronous reset.
- The counter must use exactly three flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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