Mod-N Counter with Enable: Modulus Preservation
A positive-edge-triggered Mod-5 counter increments its value by one on every LOW-to-HIGH transition of CLK when EN is HIGH, wrapping from 4 (100) to 0 (000), and holds its current value when EN is LOW. Five signals are shown: CLK (clock, period 2), EN (enable input), and the 3-bit counter state Q2, Q1, Q0 (outputs, initially 0, 1, and 0 respectively, representing state 2). Q2 is the most significant bit. Trace the state of Q2, Q1, and Q0 across all 16 time steps.
Constraints
- The counter is positive-edge-triggered and only updates state on the rising edge of
CLK. - The counter state wraps from 4 (100) directly to 0 (000).
- Changes to
ENbetween clock edges do not affect the stored state.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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